Products
IP Solutions
Esilicon’s ASIC Team is currently working on the design & development of following IP Solutions. Shortly we will be releasing these IPs (Design & Verification IPs) into Market.
- PCIE IP Gen1/2/3/4/5/6
- USB 3.0/3.1
- 10G/100G Ethernet MAC & PHY
- Display Controllers
- MIPI
- If you wish to know more details on the IP development status, availability, datasheet & pricing, please contact us at info@estdblr.com.
Training: ASIC/SoC Design Verification
- Digital Design using Verilog.
- SystemVerilog for Verification
- Methodology Trainings – UVM, OVM, VMM
- Low power UPF, CPF
- Work on latest SOC projects
- Scripting on PERL, Linux Cshell
- Python
Physical Design & Verification:
- Synthesis
- Logical Equivalence Check (LEC),
- Physical design flow including Floorplan
- Power plan, Placement
- Clock Tree Synthesis & Routing
- Static Timing Analysis
- Physical Verification and VLSI Physical Design Automation.