ASIC/SoC Design, RTL Coding and Verification
FPGA Design & Verification, Implementation, Validation & Prototyping
Synthesis, Static Timing Analysis (STA) & Design for Testability (DFT)
Formal Verification (LEC & Model Checking)
Physical Design with 22nm, 28nm, 45nm, 65nm, 90nm, 130nm, 0.18µ, 0.25µ & 0.35µ Technology nodes using Synopsys & Cadence Flows
Verification Environment, Verification Components, Testbench and Testcase Development
Functional Coverage model development
Analog Mixed Signal Design & Custom Layout
Post Silicon bring-up & validation.
Design IP & Verification IP Development